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Proceedings Paper

Simulation benchmarking for the whole resist process
Author(s): Sang-Kon Kim; Ji-Eun Lee; Seung-Wook Park; Ji-Yong Yoo; Hye-keun Oh
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Paper Abstract

A full lithography simulation has become an essential factor for semiconductor manufacturing. We have been researching all kinds of problems for lithography process by creating and using our own simulation tool, which has contributed to extracting parameters related to exposure, post exposure bake, and development. Also, its performance has been proved in comparison with other simulation tools. In this paper, our lithography simulator and some of its features are introduced. For its benchmark, we describe our own simulator’s performance and accuracy for whole resist process by the comparison of a commercial tool. The sensitivity of process parameters and process latitude due to its parameters are discussed.

Paper Details

Date Published: 29 April 2004
PDF: 7 pages
Proc. SPIE 5378, Data Analysis and Modeling for Process Control, (29 April 2004); doi: 10.1117/12.536210
Show Author Affiliations
Sang-Kon Kim, Hanyang Univ. (South Korea)
Ji-Eun Lee, Hanyang Univ. (South Korea)
Seung-Wook Park, Hanyang Univ. (South Korea)
Ji-Yong Yoo, Samsung Electronics Co., Ltd. (South Korea)
Hye-keun Oh, Hanyang Univ. (South Korea)

Published in SPIE Proceedings Vol. 5378:
Data Analysis and Modeling for Process Control
Kenneth W. Tobin, Editor(s)

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