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Proceedings Paper

Quantification of CD-SEM wafer global charging effect on CD and CD uniformity of 193-nm lithography
Author(s): Chih-Ming Ke; Hsueh-Liang Hung; Anderson Chang; Jeng-Horng Chen; Tsai-Sheng Gau; Yao-Ching Ku; Burn Jeng Lin; Tadashi Otaka; Kazuhiro Ueda; Hiroki Kawada; Hiroaki Nomura; Nelson Ren
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Paper Abstract

For 90 nm technology and below, we need to fight for every nanometer to improve the CD uniformity (CDU). New materials, especially for low-k material, bring about not only complicated integration challenges, but also new metrology difficulties such as SEM image focus failure if using low landing energy (300V) on charging wafer (e.g. -300V). The wafer global charging will also distort the CD SEM magnification and result in CD measurement error. CD SEM venders propose that the distortion be corrected by voltage contrast focus. In order to compare and quantify the measurement error correction with and without using retarding voltage focus, ArF resist non-uniform charging wafers (~ -300V) and low charging wafers (~ -7V) were prepared. Low landing energy like 300V is one of the solutions for ArF resist shrinkage. However, as the low landing energy (300V) meets the high global charging wafer (-300V), SEM cannot get sufficient secondary electron signal to construct image. Therefore, two landing voltages 500eV and 800eV were chosen for the evaluation. Three pitches 1600 nm, 460 nm and 230 nm were investigated. Two indexes are used to evaluate the wafer global charging effect on CD and CDU. One is within-wafer pitch uniformity for determining the CD SEM magnification error. The other is ArF-resist-shrinkage amplitude used to estimate the effective landing energy at charging area. The experimental results show that the pitch uniformity difference with and without using retarding focus can be larger than 2.5 nm. Similar phenomenon is also found for the line width uniformity. Resist shrinkage amplitude is significantly reduced at the highly charged area. Both results show that accurate focus procedure, i.e. retarding voltage focus employing first, is the key to reduce the CD metrology tool measurement error and improve CDU.

Paper Details

Date Published: 24 May 2004
PDF: 10 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.536147
Show Author Affiliations
Chih-Ming Ke, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Hsueh-Liang Hung, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Anderson Chang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Jeng-Horng Chen, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Tsai-Sheng Gau, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Yao-Ching Ku, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Burn Jeng Lin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Tadashi Otaka, Hitachi High-Technologies Corp. (Japan)
Kazuhiro Ueda, Hitachi High-Technologies Corp. (Japan)
Hiroki Kawada, Hitachi High-Technologies Corp. (Japan)
Hiroaki Nomura, Hitachi High-Technologies Corp. (Japan)
Nelson Ren, Hitachi High-Technologies Corp. (Japan)


Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

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