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Proceedings Paper

Taking the X Architecture to the 65-nm technology node
Author(s): Robin C. Sarma; Michael C. Smayling; Narain Arora; Toshiyuki Nagata; Michael P. Duane; Santosh Shah; Harris J. Keston; Shiany Oemardani
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Paper Abstract

The X Architecture is a new way of orienting the interconnect on an integrated circuit using diagonal pathways, as well as the traditional right-angle, or Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, the X Architecture can provide substantial improvements in chip performance, power consumption and cost. Members of the X Initiative semiconductor supply chain consortium have demonstrated the production worthiness of the X Architecture at the 130-nm and 90-nm process technology nodes. This paper presents an assessment of the manufacturing readiness of the X Architecture for the 65-nm technology node. The extent to which current production capabilities in mask writing, lithography, wafer processing, inspection and metrology can be used is discussed using the results from a 65-nm test chip. The project was a collaborative effort amongst a number of companies in the IC fabrication supply chain. Applied Materials fabricated the 65-nm X Architecture test chip at its Maydan Technology Center and leveraged the technology of other X Initiative members. Cadence Design Systems provided the test structure design and chip validation tools, Dai Nippon Printing produced the masks and Canon’s imaging system was employed for the photolithography.

Paper Details

Date Published: 3 May 2004
PDF: 8 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.536130
Show Author Affiliations
Robin C. Sarma, Cadence Design Systems, Inc. (United States)
Michael C. Smayling, Applied Materials, Inc. (United States)
Narain Arora, Cadence Design Systems, Inc. (United States)
Toshiyuki Nagata, Applied Materials, Inc. (United States)
Michael P. Duane, Applied Materials, Inc. (United States)
Santosh Shah, Cadence Design Systems, Inc. (United States)
Harris J. Keston, Applied Materials, Inc. (United States)
Shiany Oemardani, Applied Materials, Inc. (United States)


Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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