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Proceedings Paper

Approach for reducing resist footing over nonplanar wafer
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Paper Abstract

We have studied the lithography issue of resist footing in an ion implant layer after a gate conductor formation. In a previous report , we proposed the shadow model and showed a solution to reduce the resist footing. This paper reports on the further investigation into the cause and the reduction method of the resist footing over non-planar wafer with simulation and explains the effects with the shadow model. We analyzed the processes that affected the resist footing and four main effects were selected. These were NA, illumination coherency, mask bias, and mask type. We simulated these four effects on an orthogonal array by using the design of experiments (DOE). We obtained a better condition of higher NA, smaller coherency, positive mask bias, and Att-PSM for reducing the resist footing. We explain the reasons for these effective factors with the shadow model.

Paper Details

Date Published: 28 May 2004
PDF: 10 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.536108
Show Author Affiliations
Ayako Endo, Toshiba Corp. (Japan)
Takashi Sato, Toshiba Corp. (Japan)
Masafumi Asano, Toshiba Corp. (Japan)
Shoji Mimotogi, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

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