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Proceedings Paper

Manufacturability of the X Architecture at the 90-nm technology node
Author(s): Michael C. Smayling; Robin C. Sarma; Toshiyuki Nagata; Narain Arora; Michael P. Duane; Shiany Oemardani; Santosh Shah
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Paper Abstract

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.

Paper Details

Date Published: 3 May 2004
PDF: 8 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.536027
Show Author Affiliations
Michael C. Smayling, Applied Materials, Inc. (United States)
Robin C. Sarma, Cadence Design Systems, Inc. (United States)
Toshiyuki Nagata, Applied Materials, Inc. (United States)
Narain Arora, Cadence Design Systems, Inc. (United States)
Michael P. Duane, Applied Materials, Inc. (United States)
Shiany Oemardani, Applied Materials, Inc. (United States)
Santosh Shah, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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