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Proceedings Paper

Patterning capabilities of EUV resists
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Paper Abstract

EUV photoresists must be developed that meet the stringent patterning requirements for the next-generation of microprocessors (32nm node and beyond). In this paper we will address the ability of EUV photoresists to meet the material targets specs (MTS), such as CD resolution, line width roughness (LWR), photo sensitivity, and absorbance. The challenges of meeting CD resolution and line width roughness specs are not restricted to EUV lithography, but also need to be met by other technologies (193nm, 157nm, and 193 immersion technologies). However, EUV photoresists encounter the unique challenge of meeting these MTS with higher photospeeds than any other lithographic technology due to EUV source requirements. The design of EUV resists that meet all of the MTS and have sufficiently high photospeeds is very challenging. In this paper, we will present experimental results of EUV photoresists patterning results from the 10X tool at Sandia National Lab, and the F2X at Lawrence Berkeley National Lab. Data on resolution, LWR, photo sensitivity, and absorbance are included. Finally we address the capabilities of current EUV resists to meet the patterning requirements, and highlight areas where acceleration is required to meet the Intel roadmap.

Paper Details

Date Published: 14 May 2004
PDF: 9 pages
Proc. SPIE 5376, Advances in Resist Technology and Processing XXI, (14 May 2004); doi: 10.1117/12.536021
Show Author Affiliations
Wang Yueh, Intel Corp. (United States)
Heidi B. Cao, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)
Sang Lee, Intel Corp. (United States)
Michael Shumway, Univ. of California/Berkeley (United States)
Jeff Bokor, Univ. of California/Berkeley (United States)

Published in SPIE Proceedings Vol. 5376:
Advances in Resist Technology and Processing XXI
John L. Sturtevant, Editor(s)

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