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Proceedings Paper

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC
Author(s): Ji-Suk Hong; Chul-Hong Park; Dong-Hyun Kim; Soo-Han Choi; Yong-Chan Ban; Yoo-Hyon Kim; Moon-Hyun Yoo; Jeong-Taek Kong
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Paper Abstract

Sub-wavelength lithography has made the OPC (Optical Proximity Correction) technology one of the most precious commodities for the fabrication of semiconductor devices. Highly accurate gate CD (Critical Dimension) control and design rule shrinkage have become possible through the development of the OPC technology. Nevertheless, the device specifications require a more accurate gate CD control than the current OPC tools can cope with. For the model-based OPC to meet this tight CD specification, the model calibration process is very important. Current model-based OPC tools use their OPC models which usually cover the full-chip area with one universal model calibrated by comparing the empirical CD with the simulated CD of specially designed test patterns. Despite its safety, a single model for the full-chip OPC is not accurate for 2-dimensional patterns, and does not take into account the long-range effects of the patterning process such as flare noise or macro loading effect which is closely related to pattern density. In this work, we suggest a novel idea that applies the dual model to a single OPC process. We have found out that the CD trends of the patterns in the core and peripheral region of a memory chip differ from each other so that it is difficult to apply the same model for both regions. For the 110nm DRAM devices with 248nm lithography, we can reduce the gate CD variation up to 40% using the dual model OPC compared with the single model OPC. Since the dual model OPC uses two different models for a correction process, it should be carefully applied not to lose the conformity between the empirical process condition and the physical parameters of the models. The proposed dual model calibrated by the conservative modeling process reduces the gate CD variation by 50% compared with the single model OPC for a 90-nm DRAM device with 193nm lithography.

Paper Details

Date Published: 28 May 2004
PDF: 10 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.535027
Show Author Affiliations
Ji-Suk Hong, Samsung Electronics Co., Ltd. (South Korea)
Chul-Hong Park, Samsung Electronics Co., Ltd. (South Korea)
Dong-Hyun Kim, Samsung Electronics Co., Ltd. (South Korea)
Soo-Han Choi, Samsung Electronics Co., Ltd. (South Korea)
Yong-Chan Ban, Samsung Electronics Co., Ltd. (South Korea)
Yoo-Hyon Kim, Samsung Electronics Co., Ltd. (South Korea)
Moon-Hyun Yoo, Samsung Electronics Co., Ltd. (South Korea)
Jeong-Taek Kong, Samsung Electronics Co., Ltd. (South Korea)


Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

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