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Proceedings Paper

157-nm chromeless phase lithography for 45-nm SRAM gate
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Paper Abstract

157-nm lithography processes together with optimization of mask feature size and illumination conditions and chromeless mask (CLM) of mesa-type were used to fabricate a 45-nm gate by combining a high numerical aperture (NA) lens with off-axis illumination (OAI) and using Si-containing resist. It was observed that the minimum pitch for forming a 45-nm line was 140-nm. It was also shown that quadrupole illumination was the optimum OAI condition and the optimum mask feature size for forming a 45-nm line of 200-nm pitch was between 50 nm to 55 nm. In these conditions the normalized image log-slope value was about 3.0. It was demonstrated that a 45-nm SRAM gate with a depth of focus of 150 nm could be fabricated by combining these resolution enhancement techniques with high NA lithography and Si-containing resist. Furthermore the 45-nm SRAM-gate pattern was successfully transferred with a bi-layer process. From these results it was proven that fabrication of 45-nm node device could be achieved by using CLM with high NA lithography.

Paper Details

Date Published: 28 May 2004
PDF: 11 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.534897
Show Author Affiliations
Toshifumi Suganaga, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kunio Watanabe, Semiconductor Leading Edge Technologies, Inc. (Japan)
Seiji Matsuura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takuya Hagiwara, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takamitsu Furukawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshiro Itani, NEC Electronics Corp. (Japan)
Kiyoshi Fujii, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

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