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Proceedings Paper

Design rule of hole-layer for electron projection lithography
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Paper Abstract

Electron projection lithography (EPL) is a potential candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. EPL presents two key issues influencing design, because EPL uses EB and a stencil mask: beam blur and mask image placement (IP). Beam-blur deterioration depends on the Coulomb effect and is proportional to the beam current on the wafer, which depends on pattern density and the beam current on the mask. Pattern density in each subfield (SF) must be limited if the beam current on the mask is decided from throughput. IP accuracy of the stencil mask depends on the pattern layout. Intrinsic stress vanishes at openings, and distorted stress distribution causes IP error. To determine the influence of pattern layout on mask IP accuracy, simulation is checked in two steps. In the first step, simulation calculates the correlation between maximum displacement and pattern density in the entire SF. In the second step, simulation calculates the correlation between the side length of local area L and maximum additional displacement. The result of the first simulation shows that pattern deformation depends on the difference between half of the SF’s patterns density difference. To estimate the influence of pattern density imbalance in an area smaller than half of the SF, additional deformation of local area (L x L) is calculated in the second simulation step. Maximum additional displacement increases with L and pattern density. Based on the correlation between beam blur and pattern density and simulations results, the design rule (DR) for EPL is defined as the maximum pattern density in each entire SF and local area (L x L).

Paper Details

Date Published: 20 May 2004
PDF: 7 pages
Proc. SPIE 5374, Emerging Lithographic Technologies VIII, (20 May 2004); doi: 10.1117/12.534868
Show Author Affiliations
Kaoru Koike, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroshi Sakaue, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroshi Takenaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Fumihiro Koba, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takahiro Tsuchida, Semiconductor Leading Edge Technologies, Inc. (Japan)
Masaki Yamabe, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 5374:
Emerging Lithographic Technologies VIII
R. Scott Mackay, Editor(s)

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