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Proceedings Paper

Robust and efficient image processing scheme for electron beam LSI wafer pattern inspection
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Paper Abstract

Electron beam-based wafer pattern inspection systems have the major advantage of allowing for the inspection of internal electric properties. However, charge-up of the wafer resulting from the use of an electron beam significantly influences inspection and remains a challenging issue. As an alternative approach to strict charge control, the authors propose a new inspection method that is capable of error-free, one-time inspection for recipe preparation, and which provides high-efficiency defect review and low error ratio inspection. Inspection is carried out at a higher-than-expected sensitivity, and defect candidate images are stored by a defect image analyzer (DIA). After inspection, the stored information contains both actual defects and nuisance defects. The distribution of candidate defects is displayed on a wafer map and the operator reviews the stored images and high-resolution review images on demand in order to check whether defects are true or nuisance defects. If necessary, the operator then adjusts the detection sensitivity and the system re-judges the stored data, displaying the modified wafer map to screen. In this way, the proposed system is robust against sensitivity drift caused by charge-up, and offers efficient, low error ratio inspection.

Paper Details

Date Published: 24 May 2004
PDF: 10 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.534662
Show Author Affiliations
Takashi Hiroi, Hitachi, Ltd. (Japan)
Munenori Fukunishi, Hitachi, Ltd. (Japan)


Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

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