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Proceedings Paper

Metrology of LER: influence of line-edge roughness (LER) on transistor performance
Author(s): Atsuko Yamaguchi; Katsuhiko Ichinose; Satoshi Shimamoto; Hiroshi Fukuda; Ryuta Tsuchiya; Kazuhiro Ohnishi; Hiroki Kawada; Takashi Iizumi
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Paper Abstract

The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined. First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-μm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.

Paper Details

Date Published: 24 May 2004
PDF: 9 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.534631
Show Author Affiliations
Atsuko Yamaguchi, Hitachi, Ltd. (Japan)
Katsuhiko Ichinose, Hitachi, Ltd. (Japan)
Satoshi Shimamoto, Hitachi, Ltd. (Japan)
Hiroshi Fukuda, Hitachi, Ltd. (Japan)
Ryuta Tsuchiya, Hitachi, Ltd. (Japan)
Kazuhiro Ohnishi, Hitachi, Ltd. (Japan)
Hiroki Kawada, Hitachi High-Technologies Corp. (Japan)
Takashi Iizumi, Hitachi High-Technologies Corp. (Japan)


Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

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