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Proceedings Paper

Influence of line-edge roughness on MOSFET devices with sub-50-nm gates
Author(s): Kiyoshi Shibata; Naoki Izumi; Kouichirou Tsujita
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Paper Abstract

Line edge roughness (LER) poses a serious problem for the performance of MOSFET devices. In this work, we experimentally investigated the influence of LER on MOSFET devices. The conditions giving LERs were prepared with four kinds of photoresists, namely, a KrF resist and three ArF resists. We applied seven post-applied-baking (PAB)/post-exposure-baking (PEB) conditions for one of the ArF resists used in this work. We not only measured critical dimension (CD) and LER but also analyzed LER spectra with a commercially available CD SEM. As a result, we obtained the important knowledge that LER became larger as CD became finer and the trend became more marked for the transistors with larger LER. We experimentally found that LER of 9 nm at the gate length (Lg) of 50 nm increased off-state leakage (Ioff) of MOSFET, and the fluctuation of threshold voltage (Vth). Finally, we verified that LER of less than 7 nm at Lg of 50 nm is required to prevent the increase of Ioff, and that in the case of Lg of 70 nm, the fluctuation of Vth did not increase even if LER was as much as 7.5 nm.

Paper Details

Date Published: 24 May 2004
PDF: 9 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.534508
Show Author Affiliations
Kiyoshi Shibata, Semiconductor Leading Edge Technologies, Inc. (Japan)
Naoki Izumi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kouichirou Tsujita, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

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