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Proceedings Paper

On the design of multimedia software and future system architectures
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Paper Abstract

A principal challenge for reducing the cost for designing complex systems-on-chip is to pursue more generic systems for a broad range of products. For this purpose, we explore three new architectural concepts for state-of-art video applications. First, we discuss a reusable scalable hardware architecture employing a hierarchical communication network fitting with the natural hierarchy of the application. In a case study, we show that MPEG streaming in DTV occurs at high level, while subsystems communicate at lower levels. The second concept is a software design that scales over a number of processors to enable reuse over a range of VLSI process technologies. We explore this via an H.264 decoder implementation scaling nearly linearly over up to eight processors by applying data partitioning. The third topic is resource-scalability, which is required to satisfy realtime constraints in a system with a high amount of shared resources. An example complexity-scalable MPEG-2 coder scales the required cycle budget with a factor of three, in parallel with a smooth degradation of quality.

Paper Details

Date Published: 19 April 2004
PDF: 12 pages
Proc. SPIE 5309, Embedded Processors for Multimedia and Communications, (19 April 2004); doi: 10.1117/12.532564
Show Author Affiliations
Peter H. N. de With, LogicaCMG (Netherlands)
Technische Univ. Eindhoven (Netherlands)
Egbert G.T. Jaspers, Philips Research Labs. (Netherlands)

Published in SPIE Proceedings Vol. 5309:
Embedded Processors for Multimedia and Communications
Subramania I. Sudharsanan; Michael Bove; Sethuraman Panchanathan, Editor(s)

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