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Proceedings Paper

Realization of vertical P+ wall through-wafer
Author(s): J. L. Sanchez; E. Scheid; P. Austin; M. Breil; H. Carriere; Pascal Dubreuil; E. Imbernon; F. Rossel; B. Rousset
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Paper Abstract

P+ walls through wafer can be considered as key regions in the 3D architecture of new bi-directional current and voltage power integrated devices. Moreover, these P+ walls can be used as electrical vias in the design of microsystems, in order to make easier 3D packaging. In this paper, we demonstrate the possibility of fabricating these P+ walls combining the deep RIE of silicon and deposit of boron-doped polysilicon.

Paper Details

Date Published: 30 December 2003
PDF: 9 pages
Proc. SPIE 5342, Micromachining and Microfabrication Process Technology IX, (30 December 2003); doi: 10.1117/12.531533
Show Author Affiliations
J. L. Sanchez, LAAS-CNRS (France)
E. Scheid, LAAS-CNRS (France)
P. Austin, LAAS-CNRS (France)
M. Breil, LAAS-CNRS (France)
H. Carriere, LAAS-CNRS (France)
Pascal Dubreuil, LAAS-CNRS (France)
E. Imbernon, LAAS-CNRS (France)
F. Rossel, LAAS-CNRS (France)
B. Rousset, LAAS-CNRS (France)


Published in SPIE Proceedings Vol. 5342:
Micromachining and Microfabrication Process Technology IX
Mary Ann Maher; Jerome F. Jakubczak, Editor(s)

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