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Proceedings Paper

Gate-leakage-tolerant circuits in deep sub-100-nm CMOS technologies
Author(s): Sung-Mo Kang; Ge Yang; Zhongda Wang
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Paper Abstract

The leakage power consumption in deep sub-100nm CMOS systems is projected to become a significant part of the total power dissipation. Although the dual Vt CMOS process helps reduce the subthreshold leakage current, the gate leakage problem poses a significant design challenge. We introduce gate leakage tolerant circuits. We describe two new circuit techniques to suppress gate leakage currents in dual Vt Domino circuits. In standby mode, proposed circuits generate low inputs and low outputs for all Domino stages to suppress gate leakage currents in the NMOS logic tree. Simulation results using 45nm BSIM4 SPICE models for 32-bit adders show that adders using the two proposed circuits can reduce the standby gate leakage by 66% and 90%, respectively. Proposed adders have 7% active power overhead to achieve the same speed as single Vt domino adder and the area penalty is minimal with careful layout.

Paper Details

Date Published: 30 March 2004
PDF: 11 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.530278
Show Author Affiliations
Sung-Mo Kang, Univ. of California/Santa Cruz (United States)
Ge Yang, Univ. of California/Santa Cruz (United States)
Zhongda Wang, Univ. of California/Santa Cruz (United States)


Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

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