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Proceedings Paper

Comparative study on low-power high-performance standard-cell flip-flops
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Paper Abstract

This paper explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on our comparison results, transmission gate-based flip-flops show the best power-performance trade-off with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.

Paper Details

Date Published: 30 March 2004
PDF: 9 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.530225
Show Author Affiliations
Saeeid Tahmasbi Oskuii, Linkoping Univ. (Sweden)
Atila Alvandpour, Linkoping Univ. (Sweden)


Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

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