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Proceedings Paper

Low-power high-performance 2D transform coprocessor for H.264 video compression standard
Author(s): Philip P. Dang
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Paper Abstract

This paper presents a VLSI architecture and an efficient implementation of an embedded transform coprocessor for H.264 video compression standard. The proposed coprocessor was designed to work with an ARM946E-S processor. To enhance the performance, both data parallelism and pipelined architecture are utilized in the design. In this study, coprocessor was synthesized with 0.18 μm CMOS technology and its footprint is only 0.0838 mm2. Coprocessor can calculate 2-D transform for a macroblock in 30 clock cycles. The 2-D transform coprocessor dissipates 529 μW with 1.55-volt power supply at 10 MHz clock rate.

Paper Details

Date Published: 19 April 2004
PDF: 8 pages
Proc. SPIE 5309, Embedded Processors for Multimedia and Communications, (19 April 2004); doi: 10.1117/12.527227
Show Author Affiliations
Philip P. Dang, STMicroelectronics (United States)

Published in SPIE Proceedings Vol. 5309:
Embedded Processors for Multimedia and Communications
Subramania I. Sudharsanan; Michael Bove; Sethuraman Panchanathan, Editor(s)

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