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Proceedings Paper

An ultralow-noise high-speed CMOS linescan sensor for scientific and industrial applications
Author(s): Boyd A. Fowler; Janusz Balicki; Dana How; Steve Mims; John Canfield; Michael Godfrey
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Paper Abstract

This paper describes a 2048x1 linear image sensor implemented in a 0.35 μm 4M1P CMOS process that uses a low fixed pattern noise capacitive transimpedance amplifier (LFPN CTIA) pixel architecture. The pixel also includes circuitry for reducing 1/f noise, correlated double sampling, electronic shuttering, and a horizontal anti-blooming drain. High speed non-destructive readout of the sensor is achieved by using a hierarchical readout structure with two output ports. Using a JTAG interface the sensor can be programmed to operate in multiple readout modes. In the fastest readout mode, ROI, the sensor achieves 90Mpixel/sec (43.4Klines/sec) with 14e- RMS read noise. In the lowest noise mode, MRDI, with 13x oversampling of each pixel the sensor achieves 2.7Klines/sec with 1.2e- RMS read noise.

Paper Details

Date Published: 7 June 2004
PDF: 10 pages
Proc. SPIE 5301, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications V, (7 June 2004); doi: 10.1117/12.526850
Show Author Affiliations
Boyd A. Fowler, Pixel Devices International, Inc. (United States)
Janusz Balicki, Pixel Devices International, Inc. (United States)
Dana How, Pixel Devices International, Inc. (United States)
Steve Mims, Pixel Devices International, Inc. (United States)
John Canfield, Pixel Devices International, Inc. (United States)
Michael Godfrey, Pixel Devices International, Inc. (United States)


Published in SPIE Proceedings Vol. 5301:
Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications V
Nitin Sampat; Morley M. Blouke; Ricardo J. Motta, Editor(s)

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