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Proceedings Paper

Sub-5.5 FO4 delay CMOS 64-bit domino/threshold logic adder design
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Paper Abstract

This paper presents the design of a CMOS 64-bit adder using threshold logic gates based on Logical Effort (LE) transistor level delay estimation. The adder is a hybrid design, consisting of domino logic and the recently proposed Charge Recycling Threshold Logic (CRTL). The delay evaluation is based LE modeling of the delay of the domino and CRTL gates. From the initial estimations, the 8-bit sparse carry look-ahead/carry-select scheme has a delay of less than 5.5 FO4 (fan-out-of-four inverter delay), which is more than 1 FO4 delay faster than any previously published domino design.

Paper Details

Date Published: 30 March 2004
PDF: 11 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.524776
Show Author Affiliations
Peter Celinski, The Univ. of Adelaide (Australia)
Technische Univ. Delft (Netherlands)
Sorin Dan Cotofana, Technische Univ. Delft (Netherlands)
Said F. Al-Sarawi, The Univ. of Adelaide (Australia)
Derek Abbott, The Univ. of Adelaide (Australia)

Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

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