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Proceedings Paper

Interfacing methodologies for IP re-use in reconfigurable system-on-chip
Author(s): Tien-Lung Lee; Neil W. Bergmann
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Paper Abstract

Initially, IP cores in Systems-on-Chip were interconnected through custom interface logic. The more recent use of standard on-chip buses has eased integration and eliminated inefficient glue logic, and hence boosted the production of IP functional cores. However, once an IP block is designed to target a particular on-chip bus standard, retargeting to a different bus is time-consuming and tedious. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new methodology is presented that can automate the connection of an IP block to a wide variety of interface architectures with low overhead through the use a special Interface Adaptor Logic layer.

Paper Details

Date Published: 30 March 2004
PDF: 10 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.523336
Show Author Affiliations
Tien-Lung Lee, Univ. of Queensland (Australia)
Neil W. Bergmann, Univ. of Queensland (Australia)

Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

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