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Proceedings Paper

On-chip interconnect schemes for reconfigurable system-on-chip
Author(s): Andy Sheng-Han Lee; Neil W. Bergmann
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Paper Abstract

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.

Paper Details

Date Published: 30 March 2004
PDF: 12 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.523334
Show Author Affiliations
Andy Sheng-Han Lee, Univ. of Queensland (Australia)
Neil W. Bergmann, Univ. of Queensland (Australia)


Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

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