Share Email Print
cover

Proceedings Paper

Quasi-3D modeling, design, and analysis of symmetric on-chip inductors in silicon-on-sapphire technology
Author(s): Wan-Chul Kong; Said F. Al-Sarawi; Cheng-Chew Lim; Louis Wong
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A design and analysis of symmetric on-chip planar inductors are presented based in 0.5 μm silicon-on-sapphire CMOS process of Peregrine Semiconductor. Compared to conventional CMOS processes, an insulating thick sapphire (Al2O3) substrate enables higher quality factor inductors due to low energy loss in the substrate. In addition, symmetric cross-coupled configuration of identical asymmetric inductors of thick top metalization minimizes the insertion loss. Such differentially connected inductors are simulated on 2.5D electromagnetic field environment and a modeling method of quasi-3D structures is introduced for the metal strips. Maximum quality factor of 53.6 with 2.34 nH at 8.9 GHz is achieved by optimizing the symmetric circular inductors. This inductor is used in the design of a low power (0.42 mW) LC VCO operating at 5.8 GHz and exhibits a phase noise of -120.6 dBc/Hz at 3 MHz offset frequency.

Paper Details

Date Published: 30 March 2004
PDF: 8 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.522049
Show Author Affiliations
Wan-Chul Kong, The Univ. of Adelaide (Australia)
Said F. Al-Sarawi, The Univ. of Adelaide (Australia)
Cheng-Chew Lim, The Univ. of Adelaide (Australia)
Louis Wong, St. Jude Medical (United States)


Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

© SPIE. Terms of Use
Back to Top