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Proceedings Paper

A 1-GHz differential second-order low-pass sigma-delta modulator in CMOS for wireless receivers
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Paper Abstract

This paper presents the design of a 1 GHz continuous-time second order Lowpass Sigma Delta Modulator (LPSDM). The design is intended to meet the future requirements of wideband wireless receivers. The continuous-time Noise Transfer Function (NTF) for the modulator is realized using two Gm-C integrators with negative transconductance feedback and three linearized Gm elements. A three-stage delayed comparator is employed for designing the one bit quantizer, therefore a delayed NTF had to be synthesized. The presented target design is 0.18μm CMOS process. The designed chip uses both 3.3V and 1.8V MOSFETs and consumes 80mW including the clock driver and the output buffer. The performance of the modulator based on post layout simulation is 11 bits for a 5 MHz bandwidth and 8.6 bits for an 11MHz bandwidth.

Paper Details

Date Published: 30 March 2004
PDF: 12 pages
Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.521414
Show Author Affiliations
Yingbo Zhu, The Univ. of Adelaide (Australia)
Said F. Al-Sarawi, The Univ. of Adelaide (Australia)
Michael Liebelt, The Univ. of Adelaide (Australia)


Published in SPIE Proceedings Vol. 5274:
Microelectronics: Design, Technology, and Packaging
Derek Abbott; Kamran Eshraghian; Charles A. Musca; Dimitris Pavlidis; Neil Weste, Editor(s)

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