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Proceedings Paper

Speed-optimized ASIC turbo decoder core design
Author(s): XiaoYi Chen; Qingdong Yao; Peng Liu
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Paper Abstract

Turbo codes are now universally known as one of the most effective techniques for achieving performance very close to the Shannon theoretical limits in many transmission systems. This paper presents a speed optimized ASIC turbo decoder core's design. The proposed architectures achieve a complexity reduction. Because of the recursion algorithm, the result of recursion is used immediately in following cycle. A reasonable pipeline is adopted by averaged the critical path to eliminate this effect. Core is fit to realize not only in FPGA, but also can embedded into other DSP and the decode rate can reach 6 Mbps in 0.18 um technology.

Paper Details

Date Published: 28 April 2004
PDF: 7 pages
Proc. SPIE 5284, Wireless Communications and Networks, (28 April 2004); doi: 10.1117/12.520206
Show Author Affiliations
XiaoYi Chen, Zhejiang Univ. (China)
Qingdong Yao, Zhejiang Univ. (China)
Peng Liu, Zhejiang Univ. (China)

Published in SPIE Proceedings Vol. 5284:
Wireless Communications and Networks
Chih-Lin I; Jiann-An Tsai; Hequan Wu, Editor(s)

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