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Proceedings Paper

Migration of 90-nm mask and wafer lithography learning into 130-nm mask production to improve performance and yield
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Paper Abstract

Improvements in mask making techniques and metrology strategies have been required to satisfy the requirements of the 90nm technology node. With decreasing k1 and increasing MEF, critical dimension uniformity and defect specifications have faced severely tightened requirements. Many of the mask making process enhancements inspired by the 90nm node can be retrofitted into the 130nm node which improves mask quality as well as wafer-level performance. Mask critical dimension uniformity improvements directly impact wafer across chip linewidth variation which results in significantly improved chip performance. Specific examples of 130nm chip performance improvement will be discussed. Mask critical dimension and defect density improvements also result in improved mask yield and reduced mask costs. Driving 90nm mask process learning back into 130nm mask production significantly improves 130nm performance. Close interaction with the wafer lithography team allows focus on critical process window improvements for both the mask maker and wafer lithographer and allows rapid implementation of high-end process learning into older technologies.

Paper Details

Date Published: 17 December 2003
PDF: 7 pages
Proc. SPIE 5256, 23rd Annual BACUS Symposium on Photomask Technology, (17 December 2003); doi: 10.1117/12.517877
Show Author Affiliations
Andrew Watts, IBM Microelectronics Div. (United States)
Yiyang Jenny Wang, IBM Microelectronics Div. (United States)
Jed Rankin, IBM Microelectronics Div. (United States)

Published in SPIE Proceedings Vol. 5256:
23rd Annual BACUS Symposium on Photomask Technology
Kurt R. Kimmel; Wolfgang Staud, Editor(s)

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