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Proceedings Paper

Realization of a real time data flow acquisition and edge detection
Author(s): Philippe Lamaty; Federic De Melo; Cedric Munoz
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Paper Abstract

The new technologies that are CMOS sensors and most recent FPGA platform like the Xilinx Virtex-II family allow the realization of totally digital active video sensors. On the other hand, the digital visual interface (hereinafter DVI) specification provides a high-speed digital connection for visual data (T.M.D.S). These various technologies led us define a frame grabber -- processing -- display system based on three components: a CMOS sensor PB-MV13 of Photobit, a FPGA platform Virtex-II from Xilinx and a T.M.D.S transmitter SiI 160 of Silicon Image. An advantage of this realization is the suppression of the various analogue-digital conversion stages generally used to digitize and restore the video stream. The reconfiguration of the FPGA platform is another advantage, which does not limit processing to a particular purpose and simplify the conception. Besides, an important constraint of this realization is the frame definition 1280 x 1024 (SXGA) and the rate of 60 images per second with a pixel frequency of 108 MHz.

Paper Details

Date Published: 1 August 2003
PDF: 6 pages
Proc. SPIE 4948, 25th International Congress on High-Speed Photography and Photonics, (1 August 2003); doi: 10.1117/12.516724
Show Author Affiliations
Philippe Lamaty, MBDA-France (France)
Federic De Melo, Ecole Nationale Superieure d'Electronique et de ses Applications (France)
Cedric Munoz, Le2i, Univ. de Bourgogne (France)

Published in SPIE Proceedings Vol. 4948:
25th International Congress on High-Speed Photography and Photonics
Claude Cavailler; Graham P. Haddleton; Manfred Hugenschmidt, Editor(s)

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