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Proceedings Paper

Silicon-on-insulator (SOI) wafer fabrication for MEMS applications
Author(s): Bhimanadhuni R. KotiReddy; Parimi Ramaseshagiri Rao; Amitava DasGupta; Kunchinadka Narayana Hari Bhat
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Paper Abstract

In this paper, it is shown that Silicon-On-Insulator (SOI) wafers with good surface finish and thickness control can be realized using Silicon Fusion Bonding along with an optimized ethylenediamine-pyrocatechol-water (EDP) etching approach. Single crystal diaphragms of 11 μm thickness have been fabricated using these SOI wafers. These diaphragms were tested and found to withstand N2 gas pressures in excess of 260 psi without rupturing.

Paper Details

Date Published: 14 October 2003
PDF: 6 pages
Proc. SPIE 5062, Smart Materials, Structures, and Systems, (14 October 2003); doi: 10.1117/12.514719
Show Author Affiliations
Bhimanadhuni R. KotiReddy, Indian Institute of Technology, Madras (India)
Parimi Ramaseshagiri Rao, Indian Institute of Technology, Madras (India)
Amitava DasGupta, Indian Institute of Technology, Madras (India)
Kunchinadka Narayana Hari Bhat, Indian Institute of Technology, Madras (India)


Published in SPIE Proceedings Vol. 5062:
Smart Materials, Structures, and Systems

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