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Proceedings Paper

An efficient JPEG2000 encoder implemented on a platform FPGA
Author(s): Paul R. Schumacher; Mark Paluszkiewicz; Rick Ballantyne; Robert Turney
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Paper Abstract

While the recent JPEG2000 standard only specifies the bitstream and file formats to ensure interoperability, it leaves the actual implementation up to the designer. Like many DSP applications, there are a number of implementation platform options for the designer. This paper gives a complexity analysis of an implementation of a JPEG2000 encoder using a hardware/software co-design methodology on a Xilinx Virtex-II(TM) platform FPGA. Central to the performance of the encoder is a high-throughput tier-1 entropy coder. This paper will describe the encoder design targeted for video surveillance applications, and will compare and contrast with two other implementation options.

Paper Details

Date Published: 19 November 2003
PDF: 8 pages
Proc. SPIE 5203, Applications of Digital Image Processing XXVI, (19 November 2003); doi: 10.1117/12.512542
Show Author Affiliations
Paul R. Schumacher, Xilinx Research Labs. (United States)
Mark Paluszkiewicz, Xilinx Research Labs. (United States)
Rick Ballantyne, Xilinx Research Labs (United States)
Robert Turney, Xilinx Research Labs. (United States)


Published in SPIE Proceedings Vol. 5203:
Applications of Digital Image Processing XXVI
Andrew G. Tescher, Editor(s)

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