Share Email Print
cover

Proceedings Paper

Design and implementation of FIR filter by reconfigurable FPGAs for the multiwavelength optical storage system
Author(s): Ning He; Jian-ping Xiong; Changlong Jiang; Huibo Jia; Yonggui Dong
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In the multi-wavelength optical storage system, multiple data streams should be processed simultaneously. Thus a group of symmetric finite impulse response (FIR) filters are designed to meet this requirement. Unlike those conventional ways that FIR filters are implemented by digital signal processing (DSP) microprocessors or application-specific integrated circuits (ASIC), those filters are implemented on a single field programmable gate array (FPGA) integrated chip to obtain an efficient and compact solution. Since FPGAs are reconfigurable, a flexible and cost efficient platform is provided for developing the multi-signal processing subsystem. The paper presents the design and implementation of an FIR filter for the signal-processing platform using the Xilinx's SRAM-based FPGA technology. The structure and the bit serial approach of the FIR filter on an FPGA chip are also presented.

Paper Details

Date Published: 9 April 2003
PDF: 5 pages
Proc. SPIE 5060, Sixth International Symposium on Optical Storage (ISOS 2002), (9 April 2003); doi: 10.1117/12.510571
Show Author Affiliations
Ning He, Tsinghua Univ. (China)
Jian-ping Xiong, Tsinghua Univ. (China)
Changlong Jiang, Tsinghua Univ. (China)
Huibo Jia, Tsinghua Univ. (China)
Yonggui Dong, Tsinghua Univ. (China)


Published in SPIE Proceedings Vol. 5060:
Sixth International Symposium on Optical Storage (ISOS 2002)
Fuxi Gan; Zuoyi Li, Editor(s)

© SPIE. Terms of Use
Back to Top