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Proceedings Paper

High-speed clock recovery with phase-locked-loop-based on LiNbO3 modulators
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Paper Abstract

In this paper, we present a scheme for recovering 10 GHz clock from 40 Gb/s and 80 Gb/s time division multiplexed (TDM) return to zero (RZ) data stream. The proposed clock recovery is successfully demonstrated using an electrical phase locked loop (PLL). The jitter of the recovered clock is estimated to be around 50 fs. The key part in the proposed clock recovery circuit is a LiNbO3 Mach-Zehnder modulator which is shown to be highly effective in optical to electrical down conversion.

Paper Details

Date Published: 19 August 2003
PDF: 7 pages
Proc. SPIE 5247, Optical Transmission Systems and Equipment for WDM Networking II, (19 August 2003); doi: 10.1117/12.510182
Show Author Affiliations
Guanghao Zhu, Univ. of Connecticut (United States)
Hongmin Chen, Univ. of Connecticut (United States)
Qiang Wang, Univ. of Connecticut (United States)
Niloy K. Dutta, Univ. of Connecticut (United States)


Published in SPIE Proceedings Vol. 5247:
Optical Transmission Systems and Equipment for WDM Networking II
Benjamin B. Dingel; Werner Weiershausen; Achyut K. Dutta; Ken-Ichi Sato, Editor(s)

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