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Proceedings Paper

Comparison of modular multipliers on FPGAs
Author(s): Jean-Luc Beuchat; Laurent Imbert; Arnaud Tisserand
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Paper Abstract

The choice of modular multiplication algorithms for hardware implementation is not a straightforward problem. In this paper, we analyze and compare FPGA implementations of several state-of-the-art dedicated modular multipliers. For a given constant modulus M, there are several possible methods for generating an optimized modular multiplier, i.e. the dedicated (X x Y) mod M operator. Those modular multipliers can be generated using two kinds of algorithms: those that work for all values of M and those that only work for specific values of the modulo such as 2n ± 1. Several algorithms will be compared for both kind of algorithms. We also deal with two FPGA families, Virtex E and Virtex-II from Xilinx, to measure the impact of new specific built-in resources such as small embedded multipliers. The synthesizable VHDL files of the generated modular multipliers will be available on a web page.

Paper Details

Date Published: 24 December 2003
PDF: 9 pages
Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.508121
Show Author Affiliations
Jean-Luc Beuchat, Ecole Normale Superieure de Lyon, CNRS (France)
Laurent Imbert, Univ. Montpellier II, CNRS (France)
Arnaud Tisserand, Ecole Normale Superieure de Lyon, CNRS (France)


Published in SPIE Proceedings Vol. 5205:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIII
Franklin T. Luk, Editor(s)

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