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Proceedings Paper

Efficient sign extension for multiple addition
Author(s): Robert T. Grisamore; Earl E. Swartzlander Jr.
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Paper Abstract

A technique for reducing the sign extension overhead in adder trees is presented. A generalized version of the technique is shown to reduce the number of redundant sign extension computations required for reducing parallel adder trees from N terms to two terms. Additionally, the technique eliminates the fan-out latency that traditional sign extension places on late arriving sign bits. Twos complement number growth is also managed in carry-save form without the need for carry propagation. The application of the technique to 2N term adder trees is demonstrated. The implementation requires no computational overhead and needs minimal hardware. This design not only reduces hardware complexity, but also reduces computation delay. Finally, a simple circuit transformation to the traditional 4-2 compressor allows simple construction of circuits utilizing the technique.

Paper Details

Date Published: 24 December 2003
PDF: 10 pages
Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.507644
Show Author Affiliations
Robert T. Grisamore, Cicada Semiconductor Corp. (United States)
Earl E. Swartzlander Jr., Univ. of Texas at Austin (United States)

Published in SPIE Proceedings Vol. 5205:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIII
Franklin T. Luk, Editor(s)

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