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Proceedings Paper

Two-dimensional signal gating for low power in high-performance multipliers
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Paper Abstract

We propose two-dimensional signal gating for high-performance multipliers including tree multipliers and array multipliers with an upper/lower left-to-right leapfrog (ULLRLF) structure. In ULLRLF array multipliers, the G-Y gating line follows the boundary of existing upper/lower partitioning. The G-X gating line goes through the upper and lower LRLF arrays. In tree multipliers, the G-Y gating line follows the existing partitioning of tree branches. The G-X line goes through all carry-save adders for partial product reduction. Because of the irregularity of the tree reduction structure, signal gating in tree multipliers is more complex than that in array multipliers. Experimental results indicate that two-dimensional gating is quite efficient in high-performance multipliers, with 65% power reduction under test data with large dynamic range.

Paper Details

Date Published: 24 December 2003
PDF: 11 pages
Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.507366
Show Author Affiliations
Zhijun Huang, Univ. of California/Los Angeles (United States)
Milos D. Ercegovac, Univ. of California/Los Angeles (United States)


Published in SPIE Proceedings Vol. 5205:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIII
Franklin T. Luk, Editor(s)

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