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Proceedings Paper

A comparison of Dadda and Wallace multiplier delays
Author(s): Whitney J. Townsend; Earl E. Swartzlander; Jacob A. Abraham
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Paper Abstract

The two well-known fast multipliers are those presented by Wallace and Dadda. Both consist of three stages. In the first stage, the partial product matrix is formed. In the second stage, this partial product matrix is reduced to a height of two. In the final stage, these two rows are combined using a carry propagating adder. In the Wallace method, the partial products are reduced as soon as possible. In contrast, Dadda's method does the minimum reduction necessary at each level to perform the reduction in the same number of levels as required by a Wallace multiplier. It is generally assumed that, for a given size, the Wallace multiplier and the Dadda multiplier exhibit similar delay. This is because each uses the same number of pseudo adder levels to perform the partial product reduction. Although the Wallace multiplier uses a slightly smaller carry propagating adder, usually this provides no significant speed advantage. A closer examination of the delays within these two multipliers reveals this assumption to be incorrect. This paper presents a detailed analysis for several sizes of Wallace and Dadda multipliers. These results indicate that despite the presence of the larger carry propagating adder, Dadda's design yields a slightly faster multiplier.

Paper Details

Date Published: 24 December 2003
PDF: 9 pages
Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.507012
Show Author Affiliations
Whitney J. Townsend, Univ. of Texas at Austin (United States)
Earl E. Swartzlander, Univ. of Texas at Austin (United States)
Jacob A. Abraham, Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 5205:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIII
Franklin T. Luk, Editor(s)

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