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Proceedings Paper

Using truncated multipliers in DCT and IDCT hardware accelerators
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Paper Abstract

Truncated multipliers offer significant improvements in area, delay, and power. However, little research has been done on their use in actual applications, probably due to concerns about the computational errors they introduce. This paper describes a software tool used for simulating the use of truncated multipliers in DCT and IDCT hardware accelerators. Images that have been compressed and decompressed by DCT and IDCT accelerators using truncated multipliers are presented. In accelerators based on Chen's algorithm (256 multiplies per 8 x 8 block for DCT, 224 multiplies per block for IDCT), there is no visible difference between images reconstructed using truncated multipliers with 55% of the multiplication matrix eliminated and images reconstructed using standard multipliers with the same operand lengths and intermediate precision.

Paper Details

Date Published: 24 December 2003
PDF: 12 pages
Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.506793
Show Author Affiliations
E. George Walters, Lehigh Univ. (United States)
Mark G. Arnold, Lehigh Univ. (United States)
Michael J. Schulte, Univ. of Wisconsin/Madison (United States)


Published in SPIE Proceedings Vol. 5205:
Advanced Signal Processing Algorithms, Architectures, and Implementations XIII
Franklin T. Luk, Editor(s)

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