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Proceedings Paper

Faster qualification of 193-nm resists for 100-nm development using photo cell monitoring
Author(s): Chris M Jones; Chidam Kallingal; Mary T. Zawadzki; Nazneen N. Jeewakhan; Nazila N. Kaviani; Prakash Krishnan; Arthur D. Klaum; Joel Van Ess
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Paper Abstract

The development of 100-nm design rule technologies is currently taking place in many R&D facilities across the world. For some critical alyers, the transition to 193-nm resist technology has been required to meet this leading edge design rule. As with previous technology node transitions, the materials and processes available are undergoing changes and improvements as vendors encounter and solve problems. The initial implementation of the 193-nm resits process did not meet the photolithography requirements of some IC manufacturers due to very high Post Exposure Bake temperature sensitivity and consequently high wafer to wafer CD variation. The photoresist vendors have been working to improve the performance of the 193-nm resists to meet their customer's requirements. Characterization of these new resists needs to be carried out prior to implementation in the R&D line. Initial results on the second-generation resists evaluated at Cypress Semicondcutor showed better CD control compared to the aelrier resist with comparable Depth of Focus (DOF), Exposure Latitute, Etch Resistance, etc. In addition to the standard lithography parameters, resist characterization needs to include defect density studies. It was found that the new resists process with the best CD control, resulted in the introduction of orders of magnitude higher yield limiting defects at Gate, Contact adn Local Interconnect. The defect data were shared with the resists vendor and within days of the discovery the resist vendor was able to pinpoint the source of the problem. The fix was confirmed and the new resists were successfully released to production. By including defect monitoring into the resist qualification process, Cypress Semiconductor was able to 1) drive correction actions earlier resulting in faster ramp and 2) eliminate potential yield loss. We will discuss in this paper how to apply the Micro Photo Cell Monitoring methodology for defect monitoring in the photolithogprhay module and the qualification of 193nm resist processes.

Paper Details

Date Published: 2 June 2003
PDF: 11 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.504591
Show Author Affiliations
Chris M Jones, Cypress Semiconductor Corp. (United States)
Chidam Kallingal, Cypress Semiconductor Corp. (United States)
Mary T. Zawadzki, Cypress Semiconductor Corp. (United States)
Nazneen N. Jeewakhan, Cypress Semiconductor Corp. (United States)
Nazila N. Kaviani, Cypress Semiconductor Corp. (United States)
Prakash Krishnan, Cypress Semiconductor Corp. (United States)
Arthur D. Klaum, KLA-Tencor Corp. (United States)
Joel Van Ess, KLA-Tencor Corp. (United States)

Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)

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