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Proceedings Paper

Modification of existing chip layout for yield and reliability improvement by computer-aided design tools
Author(s): Mu-Jing Li; Suryanarayana Maturi; Pankaj Dixit
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Paper Abstract

A CAD flow has been developed to modify an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to correct the redundant via rule violations. It divides a large complex design into cells, so that multiple process can work concurrently as if every process were working on the top level to reach the goal in a reasonable time.

Paper Details

Date Published: 10 July 2003
PDF: 5 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.504322
Show Author Affiliations
Mu-Jing Li, Sun Microsystems, Inc. (United States)
Suryanarayana Maturi, Sun Microsystems, Inc. (United States)
Pankaj Dixit, Sun Microsystems, Inc. (United States)


Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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