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Proceedings Paper

Mask cost and cycle time reduction
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Paper Abstract

In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRS's roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation, the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.

Paper Details

Date Published: 28 August 2003
PDF: 12 pages
Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); doi: 10.1117/12.504288
Show Author Affiliations
Hong-Chang Hsieh, Taiwan Semiconductor Manufacturing Co., Ltd (Taiwan)
Johnson Chang-Cheng Hung, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Angus S. J. Chin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Sheng-Cha Lee, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Jaw-Jung Shin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Ru-Gun Liu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Burn J. Lin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 5130:
Photomask and Next-Generation Lithography Mask Technology X
Hiroyoshi Tanabe, Editor(s)

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