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Proceedings Paper

Extension of Cr-less PSM to sub 90-nm-node DRAM and logic device
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Paper Abstract

Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell and logic patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 90 nm node DRAM and logic layers concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. We also introduced concept of checkerboard CLM to apply zigzag L/S and semi dense contact in the logic layer. Using 0.75 NA ArF Scanner, CLM showed NILS reduction by 10~15% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2 μm depending on the layer. So the critical layers in sub 90 nm node DRAM satisfied 8% of EL (Exposure Latitude) and 0.3 μm of DoF (Depth of Focus) margin. Also 3D mask topographic effect of CLM in the specific contact layer was discussed.

Paper Details

Date Published: 28 August 2003
PDF: 9 pages
Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); doi: 10.1117/12.504280
Show Author Affiliations
Ju-Hyung Lee, Samsung Electronics Co., Ltd. (South Korea)
Hyung-Do Kim, Samsung Electronics Co., Ltd. (South Korea)
Dong-Hoon Chung, Samsung Electronics Co., Ltd. (South Korea)
Sang-Gyun Woo, Samsung Electronics Co., Ltd. (South Korea)
Han-Ku Cho, Samsung Electronics Co., Ltd. (South Korea)
Woo-Sung Han, Samsung Electronics Co., Ltd. (South Korea)


Published in SPIE Proceedings Vol. 5130:
Photomask and Next-Generation Lithography Mask Technology X
Hiroyoshi Tanabe, Editor(s)

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