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Proceedings Paper

Bridging nanometer design-to-manufacturing gap: automated design rules correction and silicon verification
Author(s): Linard N. Karklin; Micha Oren; Dragos Dudau; James D. Jordan
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Paper Abstract

Following Moore's Law semiconductor industry is going through a challenging transition from 180 nm to 130 nm manufacturing process geometries and rapidly approaching 90 nm geometries. The major challenges associated with the transition to nanometer design include: (1) Increasing design sizes and complexity (e.g. 300-400M transistors for FPGAs); (2) Increasing number of design rules (approaching 2000 for advanced 90 nm processes); (3) Increasing design cycle (4-9 months for ASICs); (4) Increasing design cost (advanced design flow cost $15M+). With the size and complexity of today's advanced ASICs and SoCs, the ability of designers to efficiently fix DRC errors is becoming a critical challenge impacting productivity and time-to-market. Designers need new EDA tools to process designs of very high complexity in shorter time. New tools should bridge design and process worlds by transparently providing designers with more detailed process (lithography) information. In this paper the authors will describe a method for manufacturing verification of automated design rule fixes. Many types of design rule violation are detected, automatically fixed, and verified by lithography simulation.

Paper Details

Date Published: 28 August 2003
PDF: 9 pages
Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); doi: 10.1117/12.504251
Show Author Affiliations
Linard N. Karklin, BindKey Technologies, Inc. (United States)
Micha Oren, BindKey Technologies, Inc. (United States)
Dragos Dudau, BindKey Technologies, Inc. (United States)
James D. Jordan, BindKey Technologies, Inc. (United States)


Published in SPIE Proceedings Vol. 5130:
Photomask and Next-Generation Lithography Mask Technology X
Hiroyoshi Tanabe, Editor(s)

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