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Proceedings Paper

Novel regular-array ASIC architecture for 2-D ROS sorting
Author(s): Michael F.X.B. van Swaaij; Francky V.M. Catthoor; Hugo J. De Man
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Paper Abstract

In this paper a novel regular array architecture for the 2-D running order statistics sort problem will be presented. The architecture combines a high throughput in terms of sorted windows with low hardware costs and low I/O bandwidth. It will be shown that the throughput-hardware cost ratio is substantially better than that of previously published architectures for this sorting problem under the same I/O constraints. This has been achieved by a careful design of the sorting algorithm that is tuned to match as tightly as possible the needs of real-life applications requiring this type of sorting. This design illustrates that designing algorithms with both precise applications and an architectural style in mind can greatly reduce the cost of VLSI Application Specific Integrated Circuit (ASIC) implementation. In this way it enhances the feasibility of a VLSI implementation of an algorithm.

Paper Details

Date Published: 1 November 1991
PDF: 10 pages
Proc. SPIE 1606, Visual Communications and Image Processing '91: Image Processing, (1 November 1991); doi: 10.1117/12.50365
Show Author Affiliations
Michael F.X.B. van Swaaij, IMEC (Belgium)
Francky V.M. Catthoor, IMEC (Belgium)
Hugo J. De Man, IMEC (Belgium)

Published in SPIE Proceedings Vol. 1606:
Visual Communications and Image Processing '91: Image Processing
Kou-Hu Tzou; Toshio Koga, Editor(s)

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