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Proceedings Paper

VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor
Author(s): H. Uwabu; Eiji Kakii; R. Lacombe; Masanori Maruyama; Hiroshi Fujiwara
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Paper Abstract

The CCITT Recommendation H.261 [1] describes the video coding and decoding method for the moving picture component of audiovisual services at the rates of px64 kbit/s, where p is in the range 1 to 30. Accordingly, several chip sets realizing these methods have been announced[3,4,5,6]. In this paper, a new architecture and implementation of an adaptive coding controller chip is reported. The main features of the chip include: (A) Adaptive Weighted Image Quality Control Capability, (B) High Speed Operation and (C) External Control Capability for Coding Control. The chip is implemented with CMOS standard cells and contains approximately 38,000 gates.

Paper Details

Date Published: 1 November 1991
PDF: 10 pages
Proc. SPIE 1605, Visual Communications and Image Processing '91: Visual Communication, (1 November 1991); doi: 10.1117/12.50298
Show Author Affiliations
H. Uwabu, Graphics Communication Technologies, Ltd. (Japan)
Eiji Kakii, Graphics Communication Technologies, Ltd. (Japan)
R. Lacombe, Telecom Paris (France)
Masanori Maruyama, Graphics Communication Technologies, Ltd. (Japan)
Hiroshi Fujiwara, Graphics Communication Technologies, Ltd. (Japan)


Published in SPIE Proceedings Vol. 1605:
Visual Communications and Image Processing '91: Visual Communication
Kou-Hu Tzou; Toshio Koga, Editor(s)

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