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Proceedings Paper

Approaching nanoscale integration
Author(s): Dieter Draxelmayr
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Paper Abstract

Technological progress is inevitably linked with decreasing feature size. During the past we have learned that shrinking brings many benefits: Higher speed, lower power consumption (CU²), and higher levels of integration. This manifests itself in giga-speed for processors, highly complex SoCs, and this even for battery operated products like hand-held phones. However, dark clouds are rising on the sky: Processor developers are talking about a power crisis, meaning that they don’t know how to cool their chips. Experts are stating that analog scaling has come to an end. Development and processing cost start to become overwhelming. Why does this happen and how will it continue?

Paper Details

Date Published: 21 April 2003
PDF: 12 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.501347
Show Author Affiliations
Dieter Draxelmayr, Infineon Technologies AG (Austria)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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