Share Email Print
cover

Proceedings Paper

LP-LV high-performance monolithic DTMF receiver with on-chip test facilities
Author(s): Diego Vazquez; Gloria Huertas; Maria José Avedillo; Jose María Quintana; Adoracion Rueda; Jose Luis Huertas
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Dual Tone Multi-Frequency (DTMF) signalling (also known as Touch-Tone, Tel-Touch,etc.) has gained importance in the world of telecommunications (telephony, answering machines, remote control, credit cards, etc) at the expense of dial-pulse signalling due to its more efficient and higher reliability for transmission of signals. This paper presents a high performance DTMF receiver able to operate in the range of 3V-5V of voltage supply with a low current consumption (<1mA) that is virtually fixed. In addition, on-chip test facilities for the analog part have been incorporated into the chip, in particular: a) a modified opamp (called sw-opamp) has been used to provide external accessing to inputs and outputs of the main analog blocks for off-line test purposes and, b) a Built-In-Self-Test strategy based on converting the analog part into an oscillator (the so-called oscillation-based-test) to perform a structural testing of the architecture. An integrated prototype has been designed and integrated in a 0.6μm technology. The price paid for such on-chip test facilities is very low; concretely, just an extra pin is used, power consumption during normal operation is not penalized and the area overhead is in the order of 7%. The experimental results demonstrate the good performance of the design and the feasibility of the testing approaches.

Paper Details

Date Published: 21 April 2003
PDF: 12 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.501225
Show Author Affiliations
Diego Vazquez, Instituto de Microelectronica de Sevilla-CNM (Spain)
Gloria Huertas, Instituto de Microelectronica de Sevilla-CNM (Spain)
Maria José Avedillo, Instituto de Microelectronica de Sevilla-CNM (Spain)
Jose María Quintana, Instituto de Microelectronica de Sevilla-CNM (Spain)
Adoracion Rueda, Instituto de Microelectronica de Sevilla-CNM (Spain)
Jose Luis Huertas, Instituto de Microelectronica de Sevilla-CNM (Spain)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

© SPIE. Terms of Use
Back to Top