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Proceedings Paper

High-bandwidth low-latency global interconnect
Author(s): Christer M Svensson; Peter Caputa
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Paper Abstract

Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320μm wide bus with a capacity of 160Gb/s in a nearly standard 0.18μm process.

Paper Details

Date Published: 21 April 2003
PDF: 9 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.499957
Show Author Affiliations
Christer M Svensson, Linköping Univ. (Sweden)
Peter Caputa, Linköping Univ. (Sweden)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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