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Proceedings Paper

Mixed-signal early vision chip with embedded-image and programming memories and digital I/O
Author(s): Gustavo Linan-Cembrano; Angel Rodriguez-Vazquez; Rafael Dominguez-Castro; Servando Espejo
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Paper Abstract

From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

Paper Details

Date Published: 21 April 2003
PDF: 10 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.499153
Show Author Affiliations
Gustavo Linan-Cembrano, Instituto de Microelectronica de Sevilla-CNM (Spain)
Angel Rodriguez-Vazquez, Instituto de Microelectronica de Sevilla-CNM (Spain)
Univ. de Sevilla (Spain)
Rafael Dominguez-Castro, Instituto de Microelectronica de Sevilla-CNM (Spain)
Servando Espejo, Instituto de Microelectronica de Sevilla-CNM (Spain)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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