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Proceedings Paper

Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs
Author(s): Robert C. Pack; Valery Axelrad; Andrei Shibkov; Victor V. Boksha; Judy A. Huckabay; Rachid Salik; Wolfgang Staud; Ruoping Wang; Warren D. Grobman
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Paper Abstract

Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC, alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more cost-effective application of RET.

Paper Details

Date Published: 10 July 2003
PDF: 12 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.499089
Show Author Affiliations
Robert C. Pack, Cadence Berkeley Labs. (United States)
Valery Axelrad, Sequoia Design Systems, Inc. (United States)
Andrei Shibkov, Sequoia Design Systems, Inc. (United States)
Victor V. Boksha, Sequoia Design Systems, Inc. (United States)
Judy A. Huckabay, Cadence Design Systems, Inc. (United States)
Rachid Salik, Cadence Design Systems, Inc. (United States)
Wolfgang Staud, Cadence Design Systems, Inc. (United States)
Ruoping Wang, Motorola, Inc. (United States)
Warren D. Grobman, Motorola, Inc. (United States)


Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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