Share Email Print
cover

Proceedings Paper

Optimal design of leak-proof SRAM cell using MCDM method
Author(s): Qi Wang; Sung-Mo Kang
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on microprocessor's performance. Meanwhile, it also occupies a big percentage of processor area and consumes large power. Speed, power and area of SRAM are mutually contradicting, and not easy to be met simultaneously. Many existent leakage suppression techniques have been proposed, but they limit the circuit's performance. We apply a Multi-Criteria Decision Making strategy to perform a minimum delay-power-area optimization on SRAM circuit under some certain constraints. Based on an integrated device and circuit-level approach, we search for a process that yields a targeted composite performance. In consideration of the huge amount of simulation workload involved in the optimal design-seeking process, most of this process is automated to facilitate our goal-pursuant. With varying emphasis put on delay, power or area, different optimal SRAM designs are derived and a gate-oxide thickness scaling limit is projected. The result seems to indicate that a better composite performance could be achieved under a thinner oxide thickness. Under the derived optimal oxide thickness, the static leakage power consumption contributes less than 1% in the total power dissipation.

Paper Details

Date Published: 21 April 2003
PDF: 7 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.499068
Show Author Affiliations
Qi Wang, Univ. of California/Santa Cruz (United States)
Sung-Mo Kang, Univ. of California/Santa Cruz (United States)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

© SPIE. Terms of Use
Back to Top