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Proceedings Paper

New distributed arithmetic discrete wavelet packet transform architecture
Author(s): Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Rafael Gadea; Ricardo Colom
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Paper Abstract

The present paper describes a new architecture for a Discrete Wavelet Packet Transform (DWPT) based on a folded Distributed Arithmetic (DA) implementation, which makes possible to expand two complete stages (4-subband DWPT). The proposed parameterized architecture can use different CDF wavelet coefficients with modified precision. As the distributed arithmetic technique brings the possibility to make scalable designs, the proposed architecture can be easily parameterized. The data input and coefficient precision can be increased modifying the register size and the space memory, respectively. The number of coefficients can be change too increasing the memory and replicating the register structure. Our architecture uses only two FIR filters (high-pass and low-pass) that are folded to calculate various wavelet stages together in time. A discrete DWPT implementation using CDF(9/7) wavelet coefficients are implemented on VIRTEX-E1000-6 FPGA for different precisions. Finally, the use of both, the folding technique and the DA structure has offered a frequency operation of 75 MHz with 393 Flip-flop Slices (with 8 bits precision operation) on the FPGA.

Paper Details

Date Published: 21 April 2003
PDF: 9 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.499056
Show Author Affiliations
Guillermo Paya, Univ. Politecnica de Valencia (Spain)
Marcos M. Peiro, Univ. Politecnica de Valencia (Spain)
J. Francisco Ballester, Univ. Politecnica de Valencia (Spain)
Rafael Gadea, Univ. Politecnica de Valencia (Spain)
Ricardo Colom, Univ. Politecnica de Valencia (Spain)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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