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Proceedings Paper

0.25-µm technology arithmetic codec for mobile multimedia communicators
Author(s): Alberto Alvarez; Sebastian Lopez; Jose Fco. Lopez; Roberto Sarmiento
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Paper Abstract

Low power dissipation is a must when dealing with mobile devices due to the influence related to its weight and hence, its portability. In this paper, the implementation of a 0.25 mm technology arithmetic codec with a good power/area/performance trade-off is presented. One of the key aspects introduced in order to obtain good performance is the fact of using low precision arithmetic rather than full precision, allowing the elimination of multiplications and divisions needed in order to process symbols and coefficients. These operations are replaced by shift/add operations, minimizing the complexity of the algorithm and improving the encoding and decoding process. The chip has been described in a high level language, ensuring its portability to other technologies. The implementation gives as result a 25 mm2 chip, pads included, with a total power dissipation of 300 mW and a frequency of operation of 10 MHz.

Paper Details

Date Published: 21 April 2003
PDF: 9 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.499051
Show Author Affiliations
Alberto Alvarez, Univ. de Las Palmas de Gran Canaria (Spain)
Sebastian Lopez, Univ. de Las Palmas de Gran Canaria (Spain)
Jose Fco. Lopez, Univ. de Las Palmas de Gran Canaria (Spain)
Roberto Sarmiento, Univ. de Las Palmas de Gran Canaria (Spain)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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